The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. As the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. However, in order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are used which allow greater physical thicknesses while maintaining the same effective capacitance as would be provided by a typical gate oxide used in larger technology nodes.
Additionally, as technology nodes shrink, in some IC designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate (MG) electrode to improve device performance with the decreased feature sizes. One process of forming the MG electrode is termed “gate last” process, as opposed to another MG electrode formation process termed “gate first”. The “gate last” process allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
Thus, what is desired is a method and semiconductor device providing differently configured metal gate structures for each NFET and PFET formed on a substrate.